The output stage is galvanically isolated from the USB processor and is comprised of the clocks, re-clocking circuit, and output driver.
Differential logic is the best way to implement low-jitter designs. The
Audiophilleo S/PDIF clock
and output circuits make extensive use of differential
ECL components. This approach costs more and uses somewhat more power, but enables very low
levels of jitter and switching noise.
The output circuit is galvanically isolated from both the computer and rest of the Audiophilleo, which allows coupling to the DAC without the use of an output transformer. In turn, this helps prevent ground loops which can reduce performance. The output stage also features high “return loss” below 20 MHz, so that any internal reflections are minimized; it also exhibits very clean edges, with little ringing.
Most S/PDIF devices have fixed edge transitions of up to 25 ns. The Audiophilleo1 supports a user-selectable transition from 700 ps to 15 ns (in several steps) that enables a low-jitter connection to the DAC without the use of a cable. The Audiophilleo2 is permanently set to high speed a 700 ps transition. The pop-up has all the details.
The Audiophilleo circuit board is also highly specialized, with 6 layers, and multiple, isolated ground planes. It is designed and manufactured with careful attention paid impedance control, which in turn minimizes impedance matching problems such as noise from signal reflections.